1. Field of the Invention
The present invention relates in general to integrated circuit (IC) packages and, more particularly, to a structural improvement method and means in such integrated circuit packages for preventing voids (air traps) from being generated from the unbalanced mold flow and effectively dissipating heat from the leads within the integrated circuit packages.
2. Description of the Prior Art
Integrated circuits are typically housed within a plastic package commonly referred to as a quad flat pack (QFP). Flat packs contain a lead frame, which has a plurality of leads that are connected to an integrated circuit die. The die is encapsulated by a hard plastic housing, which mechanically supports and electrically insulates the integrated circuit. The leads are typically soldered to a printed circuit board.
Packaging techniques for integrated circuits have been developed in the past in an attempt to satisfy demands for miniaturization in the integration circuit industry. Improved methods for miniaturization of integrated circuits enabling the integration of millions of transistor circuit elements into single integrated silicon embodied circuits, or chips, have resulted in increased emphasis on methods to package these circuits in an efficient amount of space.
Integrated circuits are created from a silicon wafer using various etching, doping, depositing and cutting steps that are well-known in the art of fabricating integrated circuit devices. A silicon wafer may be comprised of a number of integrated circuit dies that each represents a single integrated circuit chip. Ultimately, the chip may be packaged by transfer molding plastic encasement around the chip with a variety of pin-out or mounting and interconnection schemes. For example, M-Dip (Dual-In-Line-Plastic) provides a relatively flat, molded package having dual parallel rows of leads extending from the bottom for through-hole connection and mounting to an underlying printed circuit board. More compact integrated circuits allowing greater density on a printed circuit board are the SIP (Single-In-Line-Plastic), and SOJ (Small Outline J-leaded) molded case packages.
Typically, an array of electrical conductors called a “lead frame” is used as an interface between the integrated circuit and external circuitry for facilitating interconnection. In the case of the lead-on-chip package, the lead frame is designed to align with and connect to the integrated circuit connection pads located on a face of the integrated circuit chip. These connection pads are the points at which all input and output signals, and power and ground connections are made for the integrated circuit to function as designed.
In the case of the lead-on-chip variety of integrated circuit package, the conductors of the lead frame may be any metal suitable for bonding and may be plated, either selectively or non-selectively, as is well-known in the art. Each type of integrated circuit requires a lead frame with a specific pattern of wires. This pattern may be fabricated using etching or stamping principles well-known in the art of printed circuits. In addition to having the correct pattern for a specific integrated circuit, the lead frame must be properly aligned and held in alignment with the integrated circuit connection pads. Once aligned the lead frame may be connected to the integrated circuit connection pads by wire bonding, tape automated bonding (“TAB”), wedge bonding or other methods well-known in the art.
The lead frame is held in alignment with the integrated circuit connection pads by fixedly attaching it to the integrated circuit face having the connection pads thereon. The integrated circuit face must be insulated from the lead frame because the transistors and silicon substrate that comprise the integrated circuit are exposed and would short out if the conductive lead frame came into contact with the transistors or substrate. Therefore, insulation of some type is required between the integrated circuit face having the connection pads and the lead frame.
A three-layer sandwich consisting of a polyimide film carrier, such as Kapton (R), with adhesive on both sides has been used as a means for attaching the lead frame to the integrated circuit. Polyimide absorbs moisture which degrades the reliability of an integrated circuit package. The polyimide carrier may be as thin as 1 mil with adhesive of 0.5 mils on both sides making this sandwich a total thickness of 2 mils. Sandwich material thinner than 2 mils is difficult or impossible to handle as a single piece part during fabrication of the integrated circuit. Thus, the overall thickness of an integrated circuit package is affected by the 2 mil or greater thickness of the insulation and adhesive presently used during fabrication. Heat generated by the integrated circuit circuits must flow by thermal conduction through the 2 mil (three layer) dielectric polymer sandwich into the lead frame where the heat may be dissipated into the encapsulating package and/or into external heat conductive circuits.
Referring to FIG. 1, this figure illustrates traditional packaged integrated circuit within lead-on chip structure of the integrated circuit package. In order to conduct the thermal energy from the lead frame 60 and make the thermal energy flowing uniformly in the package successfully to achieve an object of balancing thermal mold flow, the ratio of the first mold stature H1 to the second mold stature H2 is 3:1 in the package. In this lead-on chip package, lead frame 60 is located on the parting line between the first mold 10 and the second mold 20. The part space of the first mold is occupied by chip 30 which is in the first mold 10, and therefore the space in the first mold 10 is bigger than the space in the second mold 20 to make balanceable thermal mold flow in the package.
In order to proceed with the thermal mold flow circle in the lead-on chip structural package, the length H3 between the lead frame 60 and the second mold 20 packaged material at the second axis is designed to be equal to the length H4 between the chip 30 and the first mold 10 packaged material at the second axis to avoid the process problem in the thermal mold flow in the lead-on chip structure packages. In the lead-on chip structure package, the lead frame 60 is located on the parting line between the first mold 10 and the second mold 20. There is not any means in the second mold 20 to occupy the space of the second mold 20, but there is a chip in the first mold 10 to occupy the part space of the first mold 10. In order to make the length H3 between the lead frame 60 and the second mold 20 packaged material at the second axis to be equal to the length H4 between the chip 30 and the first mold 10 packaged material at the second axis, the space of the first mold must to be broadened to follow the thickness of the chip. Accordingly, the ratio of the thickness of the first mold H1 to the thickness of the second mold H2 is 3:1 in the traditional package structure. If the thickness of the first mold and the thickness of the second mold are the same, the thermal mold flow circle will produce a problem in the packages.
When we want to reduce the volume of the integrated circuit to reduce the length between the chip and the first mold packaged material, the ratio of the length between the lead frame and the second mold packaged material to the length between the chip and the first mold packaged material cannot keep a ratio of 1:1. The thermal mold flow circle produces some voids resulting in the chip delaminating and cracking in the packages to reduce the quality of the integrated circuits.